This application claims priority to UK application 0030346.1, filed Dec. 13, 2000.
1. Field of the Invention
The present invention relates to an integrated circuit test structure. Such a test structure may be formed together with production integrated circuits on a common wafer which is divided in the usual way into individual integrated circuits with the test structure being available for testing so as to reveal any process induced defects.
2. Description of the Prior Art
As the density of integration and the size of integrated circuits increases, it becomes increasingly important to minimise the process induced defects. This is particularly so for defects associated with connections, such as contacts, vias, and portions of interconnecting layers and diffusions.
It is often very difficult to locate an open circuit fault in an integrated circuit. Techniques such as thermal imaging are of no use because an open circuit does not dissipate energy and so is not visible on a thermal image. In order to study open circuit defects, it is necessary to process representative silicon wafers on which are formed test structures. However, a typical very large scale integrated circuit may have as many as ten million contacts and six million vias and this is difficult to replicate on a practical test structure.
A requirement of a representative test structure is that it should be possible to test the structure in a reasonable time while retaining some ability to locate any defect. A single test structure containing ten million contacts in series would typically have a total resistance of 150 Mxcexa9. When tested with a typical test voltage of 2 volts, such a structure would pass a current less than 20 nA, which is so small that it would be difficult to detect whether the structure were faulty. Conversely, an array of one thousand contacts would pass a current in excess of 100 xcexcA and any failure would be easily detected. However, ten thousand such arrays would be needed to replicate ten million xe2x80x9ccellsxe2x80x9d and the typical time for testing such a structure would be about 30 minutes plus the time required to perform probe stepping.
According to the present invention, there is provided an integrated circuit test structure comprising a potential divider and at least one test circuit comprising: first and second connection chains connected in series and each comprising a plurality of integrated circuit connections connected in series; and a comparator having a first input connected to the connection between the first and second chains and a second input connected to the output of the potential divider.
The test structure may be formed on a wafer on which are formed production integrated circuits having connections of the same type as the connections of the first and second chains.
Each of the first and second chains may comprise at least one contact and/or at least one via and/or at least one portion of an interconnecting layer and/or at least one portion of an interconnection diffusion.
The potential divider and the series-connected first and second chains may be connected between first and second test voltage inputs.
The potential divider may comprise first and second resistances connected in series. The first and second resistances may have substantially the same value and the first and second chains of the or each test circuit may have substantially the same resistance. The values of the first and second resistances may be less than the resistances of the first and second chains of the or each test circuit.
The test structure may comprise a plurality of test circuits arranged as an array on a substrate. The comparators of each row may be connected to a row access input. The comparators of each column may be connected to a column access input.
The comparator of the or each test circuit may comprise a transistor. The transistor may be a field effect transistor. The transistor may be a metal oxide silicon field effect transistor. The transistor may have a gate constituting the first input and a source constituting the second input. The drains of the transistors of each column may be connected to the column access input. Each of the transistors of each row may have a further gate connected to the row access input.
It is thus possible to provide an integrated circuit test structure having a relatively simply layout and able to provide a relatively high measurement current in the case of a failure or defect, in particular of the open circuit type. The structure allows relatively fast testing. For example, in the case of an array of test circuits, the whole structure may be initially tested and, if a defect is found, the individual test circuits may then be tested. In the absence of a defect, the test time may be less than one second whereas, for a typical structure having about ten million connections, the total test time including locating the circuit containing the defect may be of the order of half a minute. A moderate level of defect location detection can be provided such that physical or xe2x80x9cvisualxe2x80x9d inspection is then viable, for example using a scanning electron microscope.